Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
P0, P1,
P2, P3
Latches
JTAG
Logic
TCK
TMS
TDI
TDO
UART1
SMBus
SPI Bus
PCA
64 kB
FLASH
256 Byte
RAM
VDD
Monitor
SFR Bus
8
0
5
1
C
o
r
e
Timers 0,
1, 2, 4
Timer 3/
RTC
P0
Drv
C
R
O
S
S
B
A
R
Port I/O
Config.
Crossbar
Config.
AV+
VDD
VDD
VDD
DGND
DGND
DGND
AGND
Reset
RST
XTAL1
XTAL2
External
Oscillator
Circuit
System
Clock
Internal
Oscillator
Digital Power
Analog Power
Debug HW
Boundary Scan
4 kB
RAM
P2.0
P2.7
P1.0/AIN1.0
P1.7/AIN1.7
P0.0
P0.7
P1
Drv
P2
Drv
Data Bus
Address Bus
Bus Control
DAC1
DAC1
(12-Bit)
VREF
DAC0
(12-Bit)
ADC
100 ksps
(10-Bit)
A
M
U
X
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
DAC0
CP0+
CP0-
CP1+
CP1-
VREF
TEMP
SENSOR
UART0
P3.0
P3.7
P3
Drv
Prog
Gain
ADC
500 ksps
(8-Bit)
A
M
U
X
8:1
MONEN
WDT
REFADC
VREFA
Prog
Gain
CP0
CP1
C
T
L
P4 Latch
D
a
t
a
P7 Latch
A
d
d
r
P5 Latch
P6 Latch
P7
DRV
P5
DRV
P6
DRV
P4
DRV
External Data Memory Bus
(REFADC)
VDD
C8051F023
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Analog Peripherals
10-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 100 ksps
-
8 external inputs; programmable as single-ended or differential
-
Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5
-
Data-dependent windowed interrupt generator
-
Built-in temperature sensor (3 C)
8-Bit ADC
-
1 LSB INL; no missing codes
-
Programmable throughput up to 500 ksps
-
8 external inputs
-
Programmable amplifier gain: 4, 2, 1, 0.5
Two 12-Bit DACs
-
Can synchronize outputs to timers for jitter-free waveform generation
Two Comparators
Internal Voltage Reference
V
DD
Monitor/Brown-out Detector
On-Chip JTAG Debug & Boundary Scan
-
On-chip debug circuitry facilitates full speed, non-intrusive in-system
debug (no emulator required)
-
Provides breakpoints, single stepping, watchpoints, stack monitor
-
Inspect/modify memory and registers
-
Superior performance to emulation systems using ICE-chips, target
pods, and sockets
-
IEEE1149.1 compliant boundary scan
High-Speed 8051 C Core
-
Pipelined instruction architecture; executes 70% of instructions in 1 or 2
system clocks
-
Up to 25 MIPS throughput with 25 MHz system clock
-
22 vectored interrupt sources
Memory
-
4352 bytes data RAM
-
64 kB Flash; in-system programmable in 512-byte sectors (512 bytes
are reserved)
-
External parallel data memory interface
Digital Peripherals
-
32 port I/O; all are 5 V tolerant
-
Hardware SMBusTM (I2CTM compatible), SPITM, and two UART serial
ports available concurrently
-
Programmable 16-bit counter/timer array with 5 capture/compare mod-
ules
-
5 general-purpose 16-bit counter/timers
-
Dedicated watchdog timer; bidirectional reset
-
Real-time clock mode using Timer 3 or PCA
Clock Sources
-
Internal programmable oscillator: 216 MHz
-
External oscillator: Crystal, RC, C, or Clock
-
Can switch between clock sources on-the-fly
Supply Voltage: 2.7 to 3.6 V
-
Typical operating current: 10 mA at 25 MHz
-
Multiple power saving sleep and shutdown modes
64-Pin TQFP
Temperature Range: 40 to +85 C
Precision Mixed Signal
Copyright 2004 by Silicon Laboratories
6.15.2004
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders
C8051F023
25 MIPS, 64 kB Flash, 10-Bit ADC, 64-Pin Mixed-Signal MCU
Selected Electrical Specifications
(T
A
= 40 to +85 C, V
DD
= 2.7 V unless otherwise specified)
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
GLOBAL CHARACTERISTICS
Digital Supply Voltage
2.7
3.6
V
Digital Supply Current
with CPU active
(V
DD
= 2.7 V)
Clock = 25 MHz
Clock = 1 MHz
Clock = 32 kHz; V
DD
Monitor Disabled
10
0.8
20
mA
mA
A
Digital Supply Current
(shutdown)
Oscillator not running; V
DD
Monitor
Enabled
Oscillator not running; V
DD
Monitor
Disabled
10
0.1
A
A
Digital Supply RAM Data
Retention Voltage
1.5 V
CPU & DIGITAL I/O PORTS
Clock Frequency Range
DC
25
MHz
Port Output High Voltage
I
OH
= -3 mA, Port I/O push-pull
V
DD
0.7
V
Port Output Low Voltage
I
OL
= 8.5 mA
0.6
V
Input High Voltage
0.7 x V
DD
V
Input Low Voltage
0.3 x V
DD
V
A/D CONVERTER
Resolution
10
bits
Integral Nonlinearity
1
LSB
Differential Nonlinearity
Guaranteed Monotonic
1
LSB
Signal-to-Noise Plus
Distortion
59
dB
Throughput Rate
100
ksps
Input Voltage Range
0
V
REF
V
COMPARATORS
Response Time
| (CP+) (CP-) | = 100 mV
4
s
Input Voltage Range
0.25
V
DD
+ 0.25
V
Input Bias Current
5
0.001
+5
nA
Input Offset Voltage
10
+10
mV
Package Information
A
A1
A2
b
D
D1
e
E
E1
-
0.05
0.95
0.17
-
-
-
-
-
-
-
-
0.22
12.00
10.00
0.50
12.00
10.00
1.20
0.15
1.05
0.27
-
-
-
-
-
MIN
(mm)
NOM
(mm)
MAX
(mm)
1
64
E
E1
e
A1
b
D
D1
PIN 1
DESIGNATOR
A2
A
C8051F020DK Development Kit
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